1. Field of the Invention
The present invention relates to a charge transfer device for use in a linear image sensor, and more specifically to an output structure of a common signal charge detection circuit for alternately picking up signal charges transferred by a pair of CCD (charge coupled device) shift registers.
2. Description of Related Art
One typical conventional linear image sensor using a CCD shift register has been disclosed in Japanese Patent Application Laid-open No. Sho 59-221176. The linear image sensor disclosed in the Japanese patent application comprises an image sensor cell array composed of a plurality of image sensor cells formed and arranged in a straight line on a semiconductor substrate of one conduction type. A pair of elongated transfer electrodes are located along the image sensor cell array and at opposite sides of the image sensor cell array. In addition, a pair of CCD shift registers are located at the outside of each of the elongated transfer electrodes and in parallel to the elongated transfer electrodes. With this arrangement, signal charges stored in the image sensor cell array are transferred to the pair of CCD shift registers under control of the elongated transfer electrodes in such a manner that signal charges stored in odd-numbered image sensor cells are transferred to a first one of the pair of CCD shift registers, and signal charges stored in even-numbered image sensor cells are transferred to a second one of the pair of CCD shift registers.
The signal charges transferred to each CCD shift register are transferred through the CCD shift register, and serially outputted from an output gate electrode provided in common adjacent to a final stage of the pair of CCD shift registers.
A floating diffusion is provided adjacent to the output gate electrode, in common to the final stage of the first CCD shift register and the final stage of the second CCD shift register. For example, the floating diffusion is in the form of a Y-shape having a first end adjacent to the final stage of the first CCD shift register through the output gate electrode, a second end adjacent to the final stage of the second CCD shift register through the output gate electrode, and a third end adjacent to a reset electrode.
With this arrangement, the signal charges transferred through the first CCD shift register and the signal charges transferred through the second CCD shift register are joined at the Y-shaped floating diffusion, so that signal charges detected in the linearly arranged image sensor cells are serially and sequentially are transferred to the Y-shaped floating diffusion in the order of the image sensor cells.
In addition, an output drain is provided adjacent to the reset electrode. The reset electrode is used to bring a potential of the floating diffusion to the same as that of the output drain before each time the signal charge is transferred to the floating diffusion. The floating diffusion is connected to a gate of a first MOS transistor, which has a drain connected to the output drain and a source connected to an output terminal and an active load formed of for example a second MOS transistor, so that a source follower is formed.
In the above mentioned signal charge detecting circuit, a detection voltage Vout obtained from the output terminal (namely, the source of the first MOS transistor) can be expressed as follows: EQU Vout={Q/(Co+C.sub.M)}.times.G (1)
where
Q is the amount of the signal electric charge flowing into the floating diffusion; PA1 G is a gain of the source follower formed of the first and second MOS transistors; PA1 Co is a capacitance of the floating diffusion; and PA1 C.sub.M is an input capacitance of the first MOS transistor.
In ordinary cases, the gain G is as low as 0.9. In addition, C.sub.M has a limit attributable to a circuit construction of the source follower. Therefore, in order to increase the output voltage Vout for a constant amount Q of the signal electric charge (namely, a electric charge/voltage conversion gain), it is necessary to decrease the capacitance Co.
Here, consider the detail of the capacitance Co. Assuming that the semiconductor substrate is of P-type and the floating diffusion is of N-type, since the signal charge output circuit operates by applying a reverse bias between the floating diffusion and the P-type substrate, a junction capacitance Csub is formed between the floating diffusion and the P-type substrate. In addition, a coupling capacitance C.sub.OG exists between the floating diffusion and the output gate electrode, and a coupling capacitance C.sub.R exists between the floating diffusion and the reset electrode.
Furthermore, since the floating diffusion is confined at both sides thereof by a pair of P-type channel stoppers, a junction capacitance Ccs is formed between the floating diffusion and each P-type channel stopper.
Therefore, the capacitance Co of the floating diffusion can be expressed: EQU Co=Csub+Ccs+C.sub.OG +C.sub.R ( 2)
However, in the conventional signal charge detection structure of the charge transfer device, it has been difficult to reduce the capacitance Co of the floating diffusion, since there has been a limit in reducing an area of the floating diffusion, for the following reason:
Namely, in the conventional signal charge detection structure of the charge transfer device, the signal charges separately outputted from one pair of CCD shift registers are caused to flow, through different channels formed under the output gates, to a common floating diffusion, as mentioned hereinbefore. Therefore, the floating diffusion has been required to be located adjacent to the output gate at two different positions. On the other hand, the floating diffusion has been required to be located adjacent to the reset electrode for resetting the floating diffusion. As a result, the floating diffusion must have been in the Y-shaped form, and therefore, there has been a limit in reducing the area of the floating diffusion.